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1997, 1999 data sheet m pd178002, 178003 mos integrated circuit the m pd178002 and 178003 are 8-bit single-chip cmos microcontrollers that incorporate hardware for digital tuning systems. the cpu uses the 78k/0 architecture, which makes it easy to implement high-speed access to internal memory and control of peripheral hardware. also, the instructions used are the high-speed 78k/0 instructions, suitable for system control. the peripheral hardware includes an input/output port, 8-bit timer, a/d converter, serial interface, power-on-clear circuits, as well as a pre-scaler for digital tuning, a pll frequency synthesizer, and a frequency counter. the m pd178p018a, one-time prom or eprom versions that can be operated in the same supply voltage range as for the mask rom versions, and various development tools, are also available. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd178003 subseries users manual: u13033e 78k/0 series users manual instructions: u12326e features ? program memory (rom) capacity m pd178002: 16 kbytes m pd178003: 24 kbytes ? data memory (ram) capacity: 512 bytes ? instruction cycle: 0.44 m s (4.5 mhz crystal resonator used) ? selected peripheral hardware of the m pd178018a subseries general-purpose i/o ports, a/d converter, serial interface, timer, frequency counter, power-on-clear circuits. ? on-chip hardware for a pll frequency synthesizer. dual modulus pre-scaler, programmable divider, phase comparator, charge pump. ? vector interrupt sources: 8 ? supply voltage: v dd = 4.5 to 5.5 v (during pll operation) v dd = 3.5 to 5.5 v (during cpu operation, when the system clock is f x /2 or lower) v dd = 4.5 to 5.5 v (during cpu operation, when the system clock is f x ) 8-bit single-chip microcontrollers document no. u12628ej3v0ds00 (3rd edition) date published december 1999 n cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd178002, 178003 2 data sheet u12628ej3v0ds00 applications car stereo, home stereo systems. ordering information part number package m pd178002gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178003gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) remark indicates rom code suffix. m pd178003 and m pd178018a subseries lineup pd178018a subseries 80 pins prom: 60 kb ram: 3 kb pd178p018a 80 pins rom: 60 kb ram: 3 kb pd178018a 80 pins rom: 48 kb ram: 3 kb pd178016a 80 pins rom: 48 kb ram: 1 kb pd178006a 80 pins rom: 32 kb ram: 1 kb pd178004a m m m m m m pd178003 subseries 80 pins rom: 24 kb ram: 0.5 kb pd178003 80 pins rom: 16 kb ram: 0.5 kb pd178002 m m m
m pd178002, 178003 3 data sheet u12628ej3v0ds00 overview of functions part number m pd178002 m pd178003 item internal rom (rom configuration) 16 kbytes (mask rom) 24 kbytes (mask rom) memory high-speed ram 512 bytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time 0.44 m s/0.88 m s/1.78 m s/3.56 m s/7.11 m s/14.22 m s (with 4.5 mhz crystal resonator used) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjust, etc. i/o port total: 62 cmos input: 1 cmos i/o: 54 n-ch open-drain i/o: 4 n-ch open-drain output: 3 a/d converter 8-bit resolution 3 channels serial interface 3-wire serial i/o mode: 1 channel timer basic timer (timer carry ff (10 hz)): 1 channel 8-bit timer/event counter: 2 channels buzzer (beep) output 1.5 khz, 3 khz, 6 khz vectored maskable internal: 5, external: 2 interrupt software 1 sources test input internal: 1 pll frequency division mode two types synthesizer direct division mode (vcol pin) pulse swallow mode (vcoh and vcol pins) reference frequency 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 khz) charge pump error out output: 2 phase comparator unlock detectable by program frequency counter frequency measurement amifc pin: for 450 khz count fmifc pin: for 450 khz/10.7 mhz count standby function halt mode stop mode reset reset by reset pin reset by power-on clear circuit (3-value detection) detection of less than 4.5 v note (cpu clock: f x ) detection of less than 3.5 v note (cpu clock: f x /2 or less and on power application) detection of less than 2.5 v note (in stop mode) supply voltage v dd = 4.5 to 5.5 v (with pll operating) v dd = 3.5 to 5.5 v (with cpu operating, cpu clock: f x /2 or less) v dd = 4.5 to 5.5 v (with cpu operating, cpu clock: f x ) package 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) one-time prom m pd178p018a note these voltage values are maximum values. the reset is actually executed at a voltage lower than these values.
m pd178002, 178003 4 data sheet u12628ej3v0ds00 table of contents 1. pin configuration (top view) ............................................................................................... .... 5 2. block diagram .............................................................................................................. ................ 7 3. pin functions .............................................................................................................. ................... 8 3.1 port pins ................................................................................................................. .................... 8 3.2 non-port pins ............................................................................................................. ................ 9 3.3 pin i/o circuits and recommended connection of unused pins ......................................... 10 4. memory space ............................................................................................................... ................. 13 5. peripheral hardware function features ........................................................................ 14 5.1 ports ..................................................................................................................... ....................... 14 5.2 clock generator ........................................................................................................... .............. 15 5.3 timer ..................................................................................................................... ...................... 15 5.4 buzzer output control circuit ............................................................................................. ..... 17 5.5 a/d converter ............................................................................................................. ................ 18 5.6 serial interfaces ......................................................................................................... ................ 19 5.7 pll frequency synthesizer ................................................................................................. ..... 20 5.8 frequency counter ......................................................................................................... ........... 21 6. interrupt functions and test functions .......................................................................... 22 6.1 interrupt functions ....................................................................................................... ............. 22 6.2 test function ............................................................................................................. ................ 25 7. standby function ........................................................................................................... ............. 26 8. reset function ............................................................................................................. ................. 26 9. instruction set ............................................................................................................ ................. 27 10. electrical specifications ................................................................................................. .... 29 11. package drawings .......................................................................................................... .......... 38 12. recommended soldering conditions ................................................................................ 39 appendix a. differences among m pd178003 and m pd178018a subseries ........................ 40 appendix b. development tools ................................................................................................ 4 1 appendix c. related documents ................................................................................................ 4 4
5 m pd178002, 178003 data sheet u12628ej3v0ds00 1. pin configuration (top view) 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178002gc- -3b9 m pd178003gc- -3b9 cautions 1. connect the ic (internally connected) pin directly to gnd. 2. connect v dd port and v dd pll pins to v dd . 3. connect the gndport and gndpll pins to gnd. 4. connect each of the regosc and regcpu pins to gnd via a 0.1 m f capacitor. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p10/ani0 p11/ani1 p12/ani2 p13 p14 p15 p20/si1 p21/so1 p22/sck1 p23 p24 p25 p26 p27 p132 p133 p134 p40 p41 p42 p37 p36/beep p35 p34/ti2 p33/ti1 p32 p31 p30 p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 p55 p54 reset v dd regosc x1 x2 gnd regcpu p06 p05 p04 p03 p02 p01/intp1 p00/intp0 p125 p124 p123 p122 p121 p120 gndport v dd port p43 p44 p45 p46 p47 amifc fmifc v dd pll vcoh vcol gndpll eo0 eo1 ic p50 p51 p52 p53 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
6 m pd178002, 178003 data sheet u12628ej3v0ds00 amifc: am intermediate frequency counter input ani0 to ani2: a/d converter input beep: buzzer output eo0, eo1: error out output fmifc: fm intermediate frequency counter input gnd: ground gndpll: pll ground gndport: port ground ic: internally connected intp0, intp1: interrupt inputs p00 to p06: port 0 p10 to p15: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p120 to p125: port 12 p132 to p134: port 13 regcpu : regulator for cpu power supply regosc : regulator for oscillator reset: reset input sck1: serial clock input/output si1: serial data input so1: serial data output ti1, ti2: timer clock input vcol, vcoh: local oscillator input v dd : power supply v dd pll: pll power supply v dd port: port power supply x1, x2: crystal resonator connection
7 m pd178002, 178003 data sheet u12628ej3v0ds00 2. block diagram remark the internal rom capacity varies depending on the product. 8-bit timer/ event counter 1 8-bit timer/ event counter 2 basic timer serial interface 1 a/d converter interrupt control buzzer output system control ram 78k/0 cpu core rom 6 6 8 8 8 8 8 6 3 3 p00 p01 to p06 frequency counter pll voltage regulator pll voltage regulator ti1/p33 ti2/p34 si1/p20 so1/p21 sck1/p22 reset x1 x2 v dd port gndport v dd reset cpu peripheral regosc regcpu gnd v osc v cpu ani0/p10 to ani2/p12 beep/p36 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 12 port 13 p10 to p15 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p120 to p125 p132 to p134 amifc fmifc eo0 eo1 vcol vcoh v dd pll gndpll ic intp0/p00 intp1/p01
8 m pd178002, 178003 data sheet u12628ej3v0ds00 3. pin functions 3.1 port pins pin name i/o function after alternate reset function p00 input port 0 input only input intp0 p01 i/o 7-bit input/output port input/output mode can be specified input intp1 p02 to p06 in 1-bit units. p10 to p12 i/o port 1 input ani0 to ani2 6-bit input/output port p13 to p15 input/output mode can be specified in 1-bit units. p20 i/o port 2 input si1 p21 8-bit input/output port so1 p22 input/output mode can be specified in 1-bit units. sck1 p23 to p27 p30 to p32 i/o port 3 input p33 8-bit input/output port ti1 p34 input/output mode can be specified in 1-bit units. ti2 p35 p36 beep p37 p40 to p47 i/o port 4 input 8-bit input/output port input/output mode can be specified in 8-bit units. the test input flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input 8-bit input/output port input/output mode can be specified in 1-bit units. p60 to p63 i/o port 6 middle voltage n-ch open-drain input 8-bit input/output port input/output port p64 to p67 input/output mode can be leds can be driven directly. specified in 1-bit units. p120 to i/o port 12 input p125 6-bit input/output port input/output mode can be specified in 1-bit units. p132 to output port 13 p134 3-bit output port n-ch open-drain output port.
9 m pd178002, 178003 data sheet u12628ej3v0ds00 3.2 non-port pins pin name i/o function after alternate reset function intp0, input external maskable interrupt input for which the valid edge (rising edge, input p00, p01 intp1 falling edge, or both rising and falling edges) can be specified. si1 input serial interface serial data input input p20 so1 output serial interface serial data output input p21 sck1 i/o serial interface serial clock input/output input p22 ti1 input external count clock input to 8-bit timer (tm1) input p33 ti2 external count clock input to 8-bit timer (tm2) p34 beep output buzzer output input p36 ani0 to input a/d converter analog input input p10 to p15 ani5 eo0, eo1 output error out output from charge pump of the pll frequency synthesizer vcol input inputs pll local band frequency (in hf, mf mode) vcoh input inputs pll local band frequency (in vhf mode) amifc input inputs am intermediate frequency counter fmifc input inputs fm intermediate frequency or am intermediate frequency counter reset input system reset input x1 input connecting crystal resonator for system clock oscillation x2 regosc oscillation regulator. connect to gnd via a 0.1 m f capacitor. ? ? regcpu ? cpu power supply regulator. connect to gnd via a 0.1 m f capacitor. ? ? v dd ? positive power supply ? ? gnd ? ground ?? v dd port ? positive power supply for port block ? ? gndport ? ground for port block ? ? v dd pll note positive power supply for pll gndpll note ground for pll ic internally connected. connect directly to gnd or gndport. note connect a capacitor of about 1000pf between the v dd pll pin and gndpll pin.
10 m pd178002, 178003 data sheet u12628ej3v0ds00 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1. table 3-1. types of pin input/output circuits pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 2 input connect to gnd or gndport. p01/intp1, p02 to p06 8 i/o set in general-purpose input port mode by software and p10/ani0 to p12/ani2 11-a independently connect to v dd , v dd port, gnd, or gndport p13 to p15 5 via a resistor. p20/si1 8 p21/so1 5 p22/sck1 8 p23 5 p24 8 p25 to p27 10 p30 to p32 5 p33/ti1, p34/ti2 8 p35 5 p36/beep p37 p40 to p47 5-g p50 to p57 5 p60 to p63 13-g p64 to p67 5 p120 to p125 p132 to p134 19 output set to low-level output by software and leave open. eo0, eo1 dts-eo1 leave open. vcol, vcoh dts-amp input set to pin disabled status by software and leave open. amifc, fmifc ic connect directly to gnd or gndport.
11 m pd178002, 178003 data sheet u12628ej3v0ds00 figure 3-1. pin input/output circuits (1/2) remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively. in in/out input enable output disable data v dd p-ch n-ch type 2 type 5 schmitt-triggered input with hysteresis characteristics type 5-g type 11-a type 10 type 8 in/out output disable data v dd p-ch n-ch in/out output disable data v dd p-ch n-ch in/out open drain output disable data v dd p-ch n-ch in/out output disable data v dd p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + _
12 m pd178002, 178003 data sheet u12628ej3v0ds00 figure 3-1. pin input/output circuits (2/2) remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively. in type 19 type 13-g type dts-amp type dts-eo1 v dd pll out n-ch dw up p-ch out v dd pll gndpll n-ch in/out input enable output disable data n-ch 5 v withstand voltage input buffer
13 m pd178002, 178003 data sheet u12628ej3v0ds00 4. memory space figure 4-1 shows the m pd178002 and 178003 memory map. figure 4-1. memory map part number last address of internal rom nnnnh m pd178002 3fffh m pd178003 5fffh note the internal rom capacity depends on the product (see the following table). special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram 512 8 bits reserved internal rom note data memory space program memory space ffffh ff00h feffh fee0h fedfh fd00h fcffh nnnnh + 1 nnnnh 0000h program area callf entry area program area callt table area vectored table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h
14 m pd178002, 178003 data sheet u12628ej3v0ds00 5. peripheral hardware function features 5.1 ports the following four types of i/o ports are available. ? cmos input (p00): 1 ? cmos input/output (p01 to p06, port 1 to port 5, p64 to p67, port 12): 54 ? n-ch open-drain input/output (p60 to p63): 4 ? n-ch open-drain output (port 13): 3 total: 62 table 5-1. port functions name pin name function port 0 p00 input only p01 to p06 input/output port. input/output can be specified in 1-bit units. port 1 p10 to p15 input/output port. input/output can be specified in 1-bit units. port 2 p20 to p27 input/output port. input/output can be specified in 1-bit units. port 3 p30 to p37 input/output port. input/output can be specified in 1-bit units. port 4 p40 to p47 input/output port. input/output can be specified in 8-bit units. the test flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 input/output port. input/output can be specified in 1-bit units. port 6 p60 to p63 n-ch open-drain input/output port. input/output can be specified in 1-bit units. leds can be driven directly. p64 to p67 input/output port. input/output can be specified in 1-bit units. port 12 p120 to p125 input/output port. input/output can be specified in 1-bit units. port 13 p132 to p134 n-ch open-drain output port.
15 m pd178002, 178003 data sheet u12628ej3v0ds00 5.2 clock generator the instruction execution time can be changed as follows. 0.44 m s/0.88 m s/1.78 m s/3.56 m s/7.11 m s/14.22 m s (4.5 mhz crystal resonator for system clock.) figure 5-1. clock generator block diagram 5.3 timer three timer channels are incorporated. basic timer: 1 channel 8-bit timer/event counter: 2 channels figure 5-2. basic timer block diagram frequency divider 4.5 mhz inttmc x1 x2 f xx prescaler system clock oscillator clock to peripheral hardware other than the above. clock to the pll frequency synthesizer, basic timer, and buzzer output control circuit. cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx prescaler selector selector f x f x 2 stop frequency divider
16 m pd178002, 178003 data sheet u12628ej3v0ds00 figure 5-3. block diagram of 8-bit timer/event counter internal bus 8-bit compare register (cr10) 8-bit timer counter 1 (tm1) clear match selector inttm1 inttm2 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer counter 2 (tm2) internal bus f xx /2 to f xx /2 f x /2 9 11 ti1/p33 f xx /2 to f xx /2 f x /2 9 11 ti2/p34
17 m pd178002, 178003 data sheet u12628ej3v0ds00 5.4 buzzer output control circuit clocks with the following frequencies can be output as buzzer (beep) output. ? 1.5 khz/3 khz/6 khz (4.5 mhz crystal resonator for system clock) figure 5-4. block diagram of buzzer output control circuit internal bus 1.5 khz 3 khz 6 khz tcl27 tcl26 tcl25 3 pm36 selector timer clock select register 2 (tcl2) (pm3) port mode register 3 beep/p36 p36 output latch
18 m pd178002, 178003 data sheet u12628ej3v0ds00 5.5 a/d converter an a/d converter consisting of three 8-bit resolution channels is incorporated. the following two a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-5. a/d converter block diagram tap selector intad v dd internal bus gnd a/d conversion result register (adcr) control circuit successive approximation register (sar) ani0/p10 ani1/p11 ani2/p12 selector sample & hold circuit voltage comparator resistor string
19 m pd178002, 178003 data sheet u12628ej3v0ds00 5.6 serial interfaces one clocked serial interface channel is incorporated. serial interface channel 1 operates in the 3-wire serial i/o mode where msb/lsb first can be switched. figure 5-6. block diagram of serial interface channel 1 internal bus interrupt request signal generator serial clock control circuit selector serial clock counter serial i/o shift register 1 (sio1) intcsi1 f xx /2 to f xx /2 8 si1/p20 so1/p21 sck1/p22
20 m pd178002, 178003 data sheet u12628ej3v0ds00 5.7 pll frequency synthesizer figure 5-7. block diagram of pll frequency synthesizer note external circuit internal bus internal bus (pllrf) (pllul) pll mode select register pll data transfer register pll ns0 pll md0 pll md1 pll rf2 pll rf1 pll rf0 pll ul0 pll reference mode register pll unlock ff judge register pll rf3 2 input select block programmable divider phase comparator ( -det) unlock ff reference frequency generator 4.5 mhz 4 charge pump eo1 eo0 vcoh (pllmd) (pllns) vcol mixer 2 f n f r pll data register (pllrl, pllrh, pllr0) f voltage control generator low pass filter note note
21 m pd178002, 178003 data sheet u12628ej3v0ds00 5.8 frequency counter figure 5-8. frequency counter block diagram internal bus ifc md0 ifc ck1 ifc ck0 ifc jg0 if counter mode select register (ifcmd) if counter gate judge register (ifcjg) if counter control register (ifcr) ifc md1 ifc res ifc st input select block start/stop control block gate time control block if counter register (ifc) block 2 2 fmifc amifc
22 m pd178002, 178003 data sheet u12628ej3v0ds00 6. interrupt functions and test functions 6.1 interrupt functions a total of 8 interrupt sources are provided, divided into the following two types. ? maskable: 7 ? software: 1 table 6-1. interrupt source list interrupt note 1 interrupt source internal/ vector basic default table configuration type priority name trigger external address type note 2 maskable 0 intp0 pin input edge detection external 0006h (a) 1 intp1 0008h (b) 2 intcsi1 end of serial interface channel 1 transfer internal 0016h (c) 3 inttmc generation of matching signal of basic timer 0018h 4 inttm1 generation of matching signal of 8-bit 001ch timer/event counter 1 5 inttm2 generation of matching signal of 8-bit 001eh timer/event counter 2 6 intad end of conversion by a/d converter 0020h software brk execution of brk instruction 003eh (d) notes 1. the default priority is a priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 6 is the lowest order. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 6-1.
m pd178002, 178003 23 data sheet u12628ej3v0ds00 figure 6-1. basic configuration of interrupt function (1/2) (a) external maskable interrupt (intp0) (b) external maskable interrupt (intp1) mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detection circuit sampling clock internal bus standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0) edge detection circuit internal bus standby release signal interrupt request
24 m pd178002, 178003 data sheet u12628ej3v0ds00 figure 6-1. basic configuration of interrupt function (2/2) (c) internal maskable interrupt (d) software interrupt priority control circuit vector table address generator internal bus interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag
m pd178002, 178003 25 data sheet u12628ej3v0ds00 6.2 test function table 6-2 shows a test function available. table 6-2. test input source list test input source name trigger internal/external intpt4 port 4 falling edge detection external figure 6-2. basic configuration of test function if: test input flag mk: test mask flag if mk internal bus test input standby release signal
26 m pd178002, 178003 data sheet u12628ej3v0ds00 7. standby function the following two standby functions are available for further reduction of system current consumption. ? halt mode: in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. ? stop mode: in this mode, oscillation of the system clock is stopped. all the operations performed on the system clock are suspended, resulting in extremely small power consumption. figure 7-1. standby function 8. reset function the following two reset methods are available. ? external reset by reset signal input ? internal reset by power on clear (poc). system clock operation stop mode (system clock oscillation stopped) halt mode (clock supply to cpu halted, oscillation maintained) interrupt request interrupt request halt instruction stop instruction
27 m pd178002, 178003 data sheet u12628ej3v0ds00 9. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a 2nd operand 1st operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc mov mov add addc sub subc and or xor cmp inc dec b,c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 rol4 [hl] mov [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
28 m pd178002, 178003 data sheet u12628ej3v0ds00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr set1 clr1 set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 2nd operand 1st operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw xchw rp note sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop
29 m pd178002, 178003 data sheet u12628ej3v0ds00 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v output withstand v bds p132 to p134 n-ch open drain C0.3 to v dd + 0.3 v voltage analog input voltage v an p10 to p12 analog input pin C0.3 to v dd + 0.3 v output current, high i oh per pin C10 ma total for p01 to p06, p30 to p37, p56, p57, C15 ma p60 to p67, p120 to p125 total for p10 to p15, p20 to p27, p40 to p47, p50 to C15 ma p55, p132 to p134 output current, low i ol note per pin peak value 15 ma rms value 7.5 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. recommended supply voltage ranges (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 during cpu operation and pll operation. 4.5 5.5 v v dd2 while the cpu is operating and the pll is stopped. 3.5 5.5 v cycle time: t cy 3 0.89 m s v dd3 while the cpu is operating and the pll is stopped. 4.5 5.5 v cycle time: t cy = 0.44 m s remark t cy : cycle time (minimum instruction execution time)
30 m pd178002, 178003 data sheet u12628ej3v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (1/3) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 p10 to p15, p21, p23, 0.7v dd v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v ih2 p00 to p06, p20, p22, 0.85v dd v dd v p24 to p27, p33, p34, reset v ih3 p60 to p63 0.7v dd v dd v (n-ch open drain) input voltage, low v il1 p10 to p15, p21, p23, 0 0.3v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v il2 p00 to p06, p20, p22, 0 0.15v dd v p24 to p27, p33, p34, reset v il3 p60 to p63 0 0.2v dd v (n-ch open drain) output voltage, high v oh1 4.5 v v dd 5.5 v, v dd C 1.0 v i oh = C1 ma 3.5 v v dd < 4.5 v, v dd C 0.5 v i oh = C100 m a output voltage, low v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v i oh = 15 ma p01 to p06, p10 to p15, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p120 to p125, p132 to p134 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, n-ch 0.2v dd v open drain, pulled-up (r = 1 k w ) remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
31 m pd178002, 178003 data sheet u12628ej3v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (2/3) parameter symbol conditions min. typ. max. unit input leakage i lih1 p00 to p06, p10 to p15, p20 to p27, v in = v dd 3 m a current, high p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lih2 p60 to p63 v in = v dd 80 m a input leakage i lil1 p00 to p06, p10 to p15, p20 to p27, v in = 0 v e3 m a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lil2 p60 to p63 e3 note m a output leakage i loh p132 to p134 v out = v dd 3 m a current, high output leakage i lol p132 to p134 v out = 0 v e3 m a current, low output off leakage i lof eo0, eo1 v out = v dd , 1 m a current v out = 0 v note when an input instruction is executed to p60 to p63, a low-level input leakage current of C200 m a (max.) flows only for one clock. at times other than this 1-clock interval, a e3 m a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. reference characteristics (t a = 25 c, v dd = 5 v) (1/2) parameter symbol conditions min. typ. max. unit output current, high i oh1 eo0 v out = v dd C 1 v C4 ma eo1 C1.8 ma output current, low i ol1 eo0 v out = 1 v 6 ma eo1 3.5 ma
32 m pd178002, 178003 data sheet u12628ej3v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (3/3) parameter symbol conditions min. typ. max. unit power supply i dd1 while the cpu is operating t cy = 0.89 m s note 2 2.5 15 ma current note 1 and the pll is stopped i dd2 f x = 4.5 mhz operation t cy = 0.44 m s note 3 4.0 27 ma v dd = 4.5 to 5.5 v i dd3 while the cpu is operating t cy = 0.89 m s note 2 0.7 1.5 ma and the pll is stopped halt mode i dd4 pin x1 sine wave t cy = 0.44 m s note 3 1.0 2.0 ma input v in = v dd . v dd = 4.5 to 5.5 v f x = 4.5 mhz operation data retention v ddr1 when the crystal oscillation t cy = 0.44 m s 4.5 5.5 v power supply voltage v ddr2 is operating t cy = 0.89 m s 3.5 5.5 v v ddr3 when the crystal oscillation is stopped 2.6 5.5 v when power off by power on clear is detected data retention i ddr1 when the crystal oscillation t a = 25 c, v dd = 5 v 2 4 m a power supply current i ddr2 is stopped 230 m a notes 1. the current flowing to the ports is not included. 2. when the processor clock control register (pcc) is set to 00h, and the oscillation mode select register (osms) is set to 00h. 3. when pcc is set to 00h and osms is set to 01h. remarks 1. t cy : cycle time (minimum instruction execution time) 2. f x : system clock oscillation frequency. reference characteristics (t a = 25 c, v dd = 5 v) (2/2) parameter symbol conditions min. typ. max. unit power supply i dd5 during cpu operation t cy = 0.44 m s note 7ma current and pll operation. vcoh pin sine wave input f in = 130 mhz, v in = 0.15 v p-p note when the processor clock control register (pcc) is set to 00h, and the oscillation mode select register (osms) is set to 01h. remark t cy : cycle time (minimum instruction execution time)
33 m pd178002, 178003 data sheet u12628ej3v0ds00 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy f xx = f x /2 note 1 , f x = 4.5 mhz operation 0.89 14.22 m s (minimum instruction f xx = f x note 2 , 4.5 v v dd 5.5 v 0.44 7.11 m s execution time) f x = 4.5 mhz operation 3.5 v v dd < 4.5 v 0.89 7.11 m s ti1, ti2 input f ti 4.5 v v dd 5.5 v 0 4.5 mhz frequency 3.5 v v dd < 4.5 v 0 275 khz ti1, ti2 input high-/ t tih , 4.5 v v dd 5.5 v 111 ns low-level width t til 3.5 v v dd < 4.5 v 1.8 m s interrupt input high-/ t inth , intp0 8/f sam note 3 m s low-level width t intl intp1 10 m s reset low level t rsl 10 m s width notes 1. when the oscillation mode select register (osms) is set to 00h. 2. when osms is set to 01h. 3. selection of f sam = f xx /2 n , f xx /32, f xx /64, f xx /128 is possible with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs) (when n = 0 to 4). remarks 1. f xx : system clock frequency (f x or f x /2) 2. f x : system clock oscillation frequency t cy vs. v dd (at f xx = f x /2 system clock operation) t cy vs. v dd (at f xx = f x system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] m 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] m
34 m pd178002, 178003 data sheet u12628ej3v0ds00 (2) serial interface (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh1 , 4.5 v v dd 5.5 v t kcy9 /2 e 50 ns t kl1 3.5 v v dd < 4.5 v t kcy9 /2 e 100 ns si1 setup time (to sck1 - )t sik1 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si1 hold time (from sck1 - )t ksi1 400 ns so1 output delay time from sck1 t kso1 c = 100 pf note 300 ns note c is the load capacitance of the so1 output line. (ii) 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh2 , 4.5 v v dd 5.5 v 400 ns t kl2 3.5 v v dd < 4.5 v 800 ns si1 setup time (to sck1 - )t sik2 100 ns si1 hold time (from sck1 - )t ksi2 400 ns so1 output delay time from sck1 t kso2 c = 100 pf note 300 ns sck1 rise/fall time t r2 , t f2 1000 ns note c is the load capacitance of the so1 output line.
35 m pd178002, 178003 data sheet u12628ej3v0ds00 t til t tih 1/f ti ti1, ti2 t intl t inth intp0, intp1 t rsl reset ac timing test points (excluding x1 input) ti timing interrupt input timing reset input timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points
36 m pd178002, 178003 data sheet u12628ej3v0ds00 serial transfer timing 3-wire serial i/o mode: t kcy1, 2 t kl1, 2 t kh1, 2 sck1 si1 so1 t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t r2 t f2
37 m pd178002, 178003 data sheet u12628ej3v0ds00 a/d converter characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit conversion overall 3.0 lsb error conversion time t conv 22.2 44.4 m s sampling time t samp 15/f xx m s analog input v ian 0v dd v voltage remarks 1. f xx : system clock frequency (f x /2) 2. f x : system clock oscillation frequency pll characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating f in1 vcol pin mf mode sine wave input v in = 0.1 v p-p 0.5 3 mhz frequency f in2 vcol pin hf mode sine wave input v in = 0.2 v p-p 9 55 mhz f in3 vcoh pin vhf mode sine wave input v in = 0.15 v p-p 60 160 mhz ifc characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating f in4 amifc pin amif count mode 0.4 0.5 mhz frequency sine wave input v in = 0.1 v p-p note f in5 fmifc pin fmif count mode 10 11 mhz sine wave input v in = 0.1 v p-p note f in6 fmifc pin amif count mode 0.4 0.5 mhz sine wave input v in = 0.1 v p-p note note the condition of a sine wave input of v in = 0.1 v p-p is the standard value of this device during standalone operation, so in consideration of the effect of noise, operation of an input amplitude condition of v in = 0.15 v p-p is recommended.
38 m pd178002, 178003 data sheet u12628ej3v0ds00 11. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 - 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h
39 m pd178002, 178003 data sheet u12628ej3v0ds00 12. recommended soldering conditions the m pd178002 and 178003 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 12-1. surface mounting type soldering conditions m pd178002gc- -3b9: 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178003gc- -3b9: 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) soldering method soldering conditions recommended condition symbol infrared reflow ir35-00-3 vps vp15-00-3 wave soldering ws60-00-1 partial heating caution do not use different soldering methods together (except for partial heating). package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c max., time: 3 seconds max. (per pin row)
40 m pd178002, 178003 data sheet u12628ej3v0ds00 appendix a. differences among m pd178003 and m pd178018a subseries product name m pd178003 subseries m pd178018a subseries items m pd178003 m pd178006a m pd178018a m pd178p018a rom 24 kbytes 48 kbytes 60 kbytes 60 kbytes (mask rom) (mask rom) (mask rom) (one-time prom) ram high-speed ram 512 bytes 1024 byte buffer ram not provided 32 bytes expanded ram not provided 2048 bytes timer 3 channels 5 channels basic timer: basic timer: 1 channel 1 channel 8-bit timer/event counter: 2 channels 8-bit timer/event 8-bit timer: 1 channel counter: 2 channels watchdog timer: 1 channel serial interface 1 channel 2 channels 3-wire mode: 3-wire/sbi/2-wire/i 2 c bus mode selectable: 1 channel 1 channel 3-wire serial i/o mode (automatic data transmit/receive function for up to 32 bytes provided on chip): 1 channel a/d converter 3 channels 6 channels d/a converter (pwm output) not provided provided eo1 pin output circuit buffer type buffer type (high impedance function not supported) (high impedance function supported)
41 m pd178002, 178003 data sheet u12628ej3v0ds00 appendix b. development tools the following development tools are available for system development using the m pd178003 subseries. also refer to (5) cautions on using development tools . (1) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df178018 device file for m pd178003 and m pd178018a subseries cc78k0-l c compiler library source file common to 78k/0 series (2) prom writing tools pg-1500 prom programmer pg-178p018gc programmer adapters connected to pg-1500 pa-178p018kk-t pg-1500 controller pg-1500 control program (3) debugging tools ? when ie-78k0-ns in-circuit emulator is used ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa note performance board for enhancing and extending the function of the ie-78k0-ns ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook pc of pc-9800 series as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at?-compatible as host machine (isa bus supported) ie-70000-pci-if interface adapter required when using a pci bus incorporated computer as host machine ie-178018-ns-em1 emulation board to emulate m pd178003, 178018a subseries np-80gc emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-3b9 type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df178018 device file for m pd178003 and m pd178018a subseries note under development
42 m pd178002, 178003 data sheet u12628ej3v0ds00 ? when ie-78001-r-a in-circuit emulator is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at-compatible as host machine (isa bus supported) ie-70000-pci-if adapter required when using a pci bus incorporated computer as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-178018-ns-em1 emulation board to emulate m pd178003, 178018a subseries ie-78k0-r-ex1 emulation probe conversion board required when using ie-178018-ns-em1 on ie-78001-r-a ie-178018-r-em emulation board to emulate m pd178003, 178018a subseries ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-3b9 type) ev-9900 tool used for removing m pd178p018akk-t from ev-9200gc-80 id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df178018 device file for m pd178003 and m pd178018a subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
43 m pd178002, 178003 data sheet u12628ej3v0ds00 (5) cautions on using development tools ? the id-78k0-ns, id78k0, and sm78k0 are used in combination with the df178018. ? the rx78k/0 is used in combination with the ra78k0 and the df178018. ? the np-80gc is a product made by naito densei machida mfg. co., ltd (tel +81-44-822-3813). contact an nec distributor regarding the purchase of this product. ? for third party development tools, see the single-chip microcontroller development tools selection guide (u11069e) . ? the host machine and os suitable for each software are as follows: host machine pc ews [os] pc-9800 series [windows?] hp9000 series 700? [hp-ux?] ibm pc/at-compatible sparcstation? [sunos? and solaris?] software [japanese/english windows] news (risc)? [news-os?] ra78k0 ? note ? cc78k0 ? note ? pg-1500 controller ? note id78k0-ns ? id78k0 ?? sm78k0 ? rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
44 m pd178002, 178003 data sheet u12628ej3v0ds00 appendix c. related documents documents related to devices document name document no. english japanese m pd178p018a data sheet u12642e u12642j m pd178003 subseries user?s manual u13033e u13033j 78k/0 series user?s manual?instruction u12326e u12326j 78k/0 series instruction set ? u10904j 78k/0 series instruction table ? u10903j 78k/0 series application note basics (ii) u10121e u10121j documents related to development tools (users manuals) document name document no. english japanese ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly u11789e u11789j language ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dos) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos) based u10540e eeu-5008 ie-78k0-ns u13731j ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-178018-ns-em1 u14012e u14012j ie-178018-r-em u10668e u10668j ep-78230 eeu-1515 eeu-985 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part u10092e u10092j user open interface specifications id78k0-ns integrated debugger windows based reference u12900e u12900j id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
45 m pd178002, 178003 data sheet u12628ej3v0ds00 documents related to embedded software (users manuals) document name document no. english japanese 78k/0 series real-time os fundamentals u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 fundamental u12257e u12257j other related documents document name document no. english japanese semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to microcomputer-related products by third party u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
46 m pd178002, 178003 data sheet u12628ej3v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
47 m pd178002, 178003 data sheet u12628ej3v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m pd178002, 178003 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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